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2017-06-28 |
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Digital Logic Design Engineer | 2 | ¼®»ç ½ÅÀÔ ~ 10³â ³»¿Ü (ÁÖÀÓ~¼±ÀÓ) | Digital logic design and verification | Çз : ¼®»ç ÀÌ»ó °æ·Â : ¼®»ç ½ÅÀÔ ~ 10³â ³»¿Ü(ÁÖÀÓ~¼±ÀÓ) SoC/IP RTL desing °¡´ÉÀÚ SoC and IP verification °¡´ÉÀÚ FPGA verification °¡´ÉÀÚ C/C++/assembly µîÀ» ÀÌ¿ëÇÑ low-level programming °æÇèÀÚ ASIC Design flow¿¡ ´ëÇÑ ÀÌÇØ Verilog, SystemVerilog, System C Áö½Ä Industry standard interface Áö½Ä [¿ì´ë»çÇ×] Synthesis, static timing analysis, DFT °¡´ÉÀÚ Multiple power domain¿¡¼ power management °æÇèÀÚ Mixed signal design °æÇèÀÚ scripting language Áö½Ä(Perl, Python, TCL, etc) Dynamic control Áö½Ä sound ½ÅÈ£ ó¸® À¯°æÇèÀÚ |
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PMIC ¼³°è | 1 | 10³â ÀÌ»ó (¼±ÀÓ ÀÌ»ó) | AMOLED DCDC Converter °³¹ß | Çз : ¼®»ç ÀÌ»ó Analog ȸ·Î¼³°è Àü°ø DCDC Converter °³¹ß 10³â ÀÌ»ó [¿ì´ë»çÇ×] DCDC Converter ȸ·Î¼³°è ¹× ¸ðµ¨¸µ Àü°ø |
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